Dynamic Fault Diagnosis on Reconfigurable Hardware

In this paper, we introduce a new approach for locating and diagnosing faults in combinational circuits. The approach is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the combinational circuit under diagnosis (CUD). This approach eliminates the need for large storage required by a software based fault diagnosis. In this paper, we show the approach's feasibility in terms of hardware resources, speed, and how it compares with software based techniques

SYSTEM-ON-CHIP POWER CONSUMPTION REFINEMENT AND ANALYSIS

Accurate power consumption estimation of a System-on-Chip (SoC) using modeling techniques is difficult due to the diverse mixture of processes with radically different current consumption. It is very important that these estimations will be fine tuned to the specific SoC with accurate current measurement during the design and prototyping phase. We introduce an accurate method to measure power consumption using a single measurement point and a dynamic logging algorithm. We present a demonstration tool for continuous logging of the instantaneous power consumption with an identification of the running process within the SoC. Our approach can also be used to steer the dynamic power management (DPM) of a SoC. 1